Module core::arch::arm[][src]

🔬 This is a nightly-only experimental API. (stdsimd #27731)
This is supported on ARM only.

Platform-specific intrinsics for the arm platform.

See the module documentation for more details.

Structs

APSRExperimental

Application Program Status Register

SYExperimental

Full system is the required shareability domain, reads and writes are the required access types

float32x2_tExperimental

ARM-specific 64-bit wide vector of two packed f32.

float32x4_tExperimental

ARM-specific 128-bit wide vector of four packed f32.

int8x4_tExperimental

ARM-specific 32-bit wide vector of four packed i8.

int8x8_tExperimental

ARM-specific 64-bit wide vector of eight packed i8.

int8x8x2_tExperimental

ARM-specific type containing two int8x8_t vectors.

int8x8x3_tExperimental

ARM-specific type containing three int8x8_t vectors.

int8x8x4_tExperimental

ARM-specific type containing four int8x8_t vectors.

int8x16_tExperimental

ARM-specific 128-bit wide vector of sixteen packed i8.

int16x2_tExperimental

ARM-specific 32-bit wide vector of two packed i16.

int16x4_tExperimental

ARM-specific 64-bit wide vector of four packed i16.

int16x8_tExperimental

ARM-specific 128-bit wide vector of eight packed i16.

int32x2_tExperimental

ARM-specific 64-bit wide vector of two packed i32.

int32x4_tExperimental

ARM-specific 128-bit wide vector of four packed i32.

int64x1_tExperimental

ARM-specific 64-bit wide vector of one packed i64.

int64x2_tExperimental

ARM-specific 128-bit wide vector of two packed i64.

poly8x8_tExperimental

ARM-specific 64-bit wide polynomial vector of eight packed p8.

poly8x8x2_tExperimental

ARM-specific type containing two poly8x8_t vectors.

poly8x8x3_tExperimental

ARM-specific type containing three poly8x8_t vectors.

poly8x8x4_tExperimental

ARM-specific type containing four poly8x8_t vectors.

poly8x16_tExperimental

ARM-specific 128-bit wide vector of sixteen packed p8.

poly16x4_tExperimental

ARM-specific 64-bit wide vector of four packed p16.

poly16x8_tExperimental

ARM-specific 128-bit wide vector of eight packed p16.

poly64x1_tExperimental

ARM-specific 64-bit wide vector of one packed p64.

poly64x2_tExperimental

ARM-specific 128-bit wide vector of two packed p64.

uint8x4_tExperimental

ARM-specific 32-bit wide vector of four packed u8.

uint8x8_tExperimental

ARM-specific 64-bit wide vector of eight packed u8.

uint8x8x2_tExperimental

ARM-specific type containing two uint8x8_t vectors.

uint8x8x3_tExperimental

ARM-specific type containing three uint8x8_t vectors.

uint8x8x4_tExperimental

ARM-specific type containing four uint8x8_t vectors.

uint8x16_tExperimental

ARM-specific 128-bit wide vector of sixteen packed u8.

uint16x2_tExperimental

ARM-specific 32-bit wide vector of two packed u16.

uint16x4_tExperimental

ARM-specific 64-bit wide vector of four packed u16.

uint16x8_tExperimental

ARM-specific 128-bit wide vector of eight packed u16.

uint32x2_tExperimental

ARM-specific 64-bit wide vector of two packed u32.

uint32x4_tExperimental

ARM-specific 128-bit wide vector of four packed u32.

uint64x1_tExperimental

ARM-specific 64-bit wide vector of one packed u64.

uint64x2_tExperimental

ARM-specific 128-bit wide vector of two packed u64.

Functions

__breakpointExperimental

Inserts a breakpoint instruction.

__dmbExperimental

Generates a DMB (data memory barrier) instruction or equivalent CP15 instruction.

__dsbExperimental

Generates a DSB (data synchronization barrier) instruction or equivalent CP15 instruction.

__isbExperimental

Generates an ISB (instruction synchronization barrier) instruction or equivalent CP15 instruction.

__ldrexExperimental

Executes a exclusive LDR instruction for 32 bit value.

__nopExperimental

Generates an unspecified no-op instruction.

__qaddExperimental

Signed saturating addition

__qadd8Experimental

Saturating four 8-bit integer additions

__qadd16Experimental

Saturating two 16-bit integer additions

__qasxExperimental

Returns the 16-bit signed saturated equivalent of

__qdblExperimental

Insert a QADD instruction

__qsaxExperimental

Returns the 16-bit signed saturated equivalent of

__qsubExperimental

Signed saturating subtraction

__qsub8Experimental

Saturating two 8-bit integer subtraction

__qsub16Experimental

Saturating two 16-bit integer subtraction

__rsrExperimental

Reads a 32-bit system register

__rsrpExperimental

Reads a system register containing an address

__sadd8Experimental

Returns the 8-bit signed saturated equivalent of

__sadd16Experimental

Returns the 16-bit signed saturated equivalent of

__sasxExperimental

Returns the 16-bit signed equivalent of

__selExperimental

Select bytes from each operand according to APSR GE flags

__sevExperimental

Generates a SEV (send a global event) hint instruction.

__shadd8Experimental

Signed halving parallel byte-wise addition.

__shadd16Experimental

Signed halving parallel halfword-wise addition.

__shsub8Experimental

Signed halving parallel byte-wise subtraction.

__shsub16Experimental

Signed halving parallel halfword-wise subtraction.

__smlabbExperimental

Insert a SMLABB instruction

__smlabtExperimental

Insert a SMLABT instruction

__smladExperimental

Dual 16-bit Signed Multiply with Addition of products and 32-bit accumulation.

__smlatbExperimental

Insert a SMLATB instruction

__smlattExperimental

Insert a SMLATT instruction

__smlawbExperimental

Insert a SMLAWB instruction

__smlawtExperimental

Insert a SMLAWT instruction

__smlsdExperimental

Dual 16-bit Signed Multiply with Subtraction of products and 32-bit accumulation and overflow detection.

__smuadExperimental

Signed Dual Multiply Add.

__smuadxExperimental

Signed Dual Multiply Add Reversed.

__smulbbExperimental

Insert a SMULBB instruction

__smulbtExperimental

Insert a SMULTB instruction

__smultbExperimental

Insert a SMULTB instruction

__smulttExperimental

Insert a SMULTT instruction

__smulwbExperimental

Insert a SMULWB instruction

__smulwtExperimental

Insert a SMULWT instruction

__smusdExperimental

Signed Dual Multiply Subtract.

__smusdxExperimental

Signed Dual Multiply Subtract Reversed.

__ssub8Experimental

Inserts a SSUB8 instruction.

__strexExperimental

Executes a exclusive STR instruction for 32 bit values

__usad8Experimental

Sum of 8-bit absolute differences.

__usada8Experimental

Sum of 8-bit absolute differences and constant.

__usub8Experimental

Inserts a USUB8 instruction.

__wfeExperimental

Generates a WFE (wait for event) hint instruction, or nothing.

__wfiExperimental

Generates a WFI (wait for interrupt) hint instruction, or nothing.

__wsrExperimental

Writes a 32-bit system register

__wsrpExperimental

Writes a system register containing an address

__yieldExperimental

Generates a YIELD hint instruction.

_rev_u16Experimental

Reverse the order of the bytes.

_rev_u32Experimental

Reverse the order of the bytes.

udfExperimental

Generates the trap instruction UDF

vabs_s8Experimentalneon and v7

Absolute value (wrapping).

vabs_s16Experimentalneon and v7

Absolute value (wrapping).

vabs_s32Experimentalneon and v7

Absolute value (wrapping).

vabsq_s8Experimentalneon and v7

Absolute value (wrapping).

vabsq_s16Experimentalneon and v7

Absolute value (wrapping).

vabsq_s32Experimentalneon and v7

Absolute value (wrapping).

vadd_f32Experimentalneon and v7

Vector add.

vadd_s8Experimentalneon and v7

Vector add.

vadd_s16Experimentalneon and v7

Vector add.

vadd_s32Experimentalneon and v7

Vector add.

vadd_u8Experimentalneon and v7

Vector add.

vadd_u16Experimentalneon and v7

Vector add.

vadd_u32Experimentalneon and v7

Vector add.

vaddhn_high_s16Experimentalneon and v7

Add returning High Narrow (high half).

vaddhn_high_s32Experimentalneon and v7

Add returning High Narrow (high half).

vaddhn_high_s64Experimentalneon and v7

Add returning High Narrow (high half).

vaddhn_high_u16Experimentalneon and v7

Add returning High Narrow (high half).

vaddhn_high_u32Experimentalneon and v7

Add returning High Narrow (high half).

vaddhn_high_u64Experimentalneon and v7

Add returning High Narrow (high half).

vaddhn_s16Experimentalneon and v7

Add returning High Narrow.

vaddhn_s32Experimentalneon and v7

Add returning High Narrow.

vaddhn_s64Experimentalneon and v7

Add returning High Narrow.

vaddhn_u16Experimentalneon and v7

Add returning High Narrow.

vaddhn_u32Experimentalneon and v7

Add returning High Narrow.

vaddhn_u64Experimentalneon and v7

Add returning High Narrow.

vaddl_high_s8Experimentalneon and v7

Signed Add Long (vector, high half).

vaddl_high_s16Experimentalneon and v7

Signed Add Long (vector, high half).

vaddl_high_s32Experimentalneon and v7

Signed Add Long (vector, high half).

vaddl_high_u8Experimentalneon and v7

Unsigned Add Long (vector, high half).

vaddl_high_u16Experimentalneon and v7

Unsigned Add Long (vector, high half).

vaddl_high_u32Experimentalneon and v7

Unsigned Add Long (vector, high half).

vaddl_s8Experimentalneon and v7

Signed Add Long (vector).

vaddl_s16Experimentalneon and v7

Signed Add Long (vector).

vaddl_s32Experimentalneon and v7

Signed Add Long (vector).

vaddl_u8Experimentalneon and v7

Unsigned Add Long (vector).

vaddl_u16Experimentalneon and v7

Unsigned Add Long (vector).

vaddl_u32Experimentalneon and v7

Unsigned Add Long (vector).

vaddq_f32Experimentalneon and v7

Vector add.

vaddq_s8Experimentalneon and v7

Vector add.

vaddq_s16Experimentalneon and v7

Vector add.

vaddq_s32Experimentalneon and v7

Vector add.

vaddq_s64Experimentalneon and v7

Vector add.

vaddq_u8Experimentalneon and v7

Vector add.

vaddq_u16Experimentalneon and v7

Vector add.

vaddq_u32Experimentalneon and v7

Vector add.

vaddq_u64Experimentalneon and v7

Vector add.

vaddw_high_s8Experimentalneon and v7

Signed Add Wide (high half).

vaddw_high_s16Experimentalneon and v7

Signed Add Wide (high half).

vaddw_high_s32Experimentalneon and v7

Signed Add Wide (high half).

vaddw_high_u8Experimentalneon and v7

Unsigned Add Wide (high half).

vaddw_high_u16Experimentalneon and v7

Unsigned Add Wide (high half).

vaddw_high_u32Experimentalneon and v7

Unsigned Add Wide (high half).

vaddw_s8Experimentalneon and v7

Signed Add Wide.

vaddw_s16Experimentalneon and v7

Signed Add Wide.

vaddw_s32Experimentalneon and v7

Signed Add Wide.

vaddw_u8Experimentalneon and v7

Unsigned Add Wide.

vaddw_u16Experimentalneon and v7

Unsigned Add Wide.

vaddw_u32Experimentalneon and v7

Unsigned Add Wide.

vand_s8Experimentalneon and v7

Vector bitwise and

vand_s16Experimentalneon and v7

Vector bitwise and

vand_s32Experimentalneon and v7

Vector bitwise and

vand_s64Experimentalneon and v7

Vector bitwise and

vand_u8Experimentalneon and v7

Vector bitwise and

vand_u16Experimentalneon and v7

Vector bitwise and

vand_u32Experimentalneon and v7

Vector bitwise and

vand_u64Experimentalneon and v7

Vector bitwise and

vandq_s8Experimentalneon and v7

Vector bitwise and

vandq_s16Experimentalneon and v7

Vector bitwise and

vandq_s32Experimentalneon and v7

Vector bitwise and

vandq_s64Experimentalneon and v7

Vector bitwise and

vandq_u8Experimentalneon and v7

Vector bitwise and

vandq_u16Experimentalneon and v7

Vector bitwise and

vandq_u32Experimentalneon and v7

Vector bitwise and

vandq_u64Experimentalneon and v7

Vector bitwise and

vceq_f32Experimentalneon and v7

Floating-point compare equal

vceq_s8Experimentalneon and v7

Compare bitwise Equal (vector)

vceq_s16Experimentalneon and v7

Compare bitwise Equal (vector)

vceq_s32Experimentalneon and v7

Compare bitwise Equal (vector)

vceq_u8Experimentalneon and v7

Compare bitwise Equal (vector)

vceq_u16Experimentalneon and v7

Compare bitwise Equal (vector)

vceq_u32Experimentalneon and v7

Compare bitwise Equal (vector)

vceqq_f32Experimentalneon and v7

Floating-point compare equal

vceqq_s8Experimentalneon and v7

Compare bitwise Equal (vector)

vceqq_s16Experimentalneon and v7

Compare bitwise Equal (vector)

vceqq_s32Experimentalneon and v7

Compare bitwise Equal (vector)

vceqq_u8Experimentalneon and v7

Compare bitwise Equal (vector)

vceqq_u16Experimentalneon and v7

Compare bitwise Equal (vector)

vceqq_u32Experimentalneon and v7

Compare bitwise Equal (vector)

vcge_f32Experimentalneon and v7

Floating-point compare greater than or equal

vcge_s8Experimentalneon and v7

Compare signed greater than or equal

vcge_s16Experimentalneon and v7

Compare signed greater than or equal

vcge_s32Experimentalneon and v7

Compare signed greater than or equal

vcge_u8Experimentalneon and v7

Compare unsigned greater than or equal

vcge_u16Experimentalneon and v7

Compare unsigned greater than or equal

vcge_u32Experimentalneon and v7

Compare unsigned greater than or equal

vcgeq_f32Experimentalneon and v7

Floating-point compare greater than or equal

vcgeq_s8Experimentalneon and v7

Compare signed greater than or equal

vcgeq_s16Experimentalneon and v7

Compare signed greater than or equal

vcgeq_s32Experimentalneon and v7

Compare signed greater than or equal

vcgeq_u8Experimentalneon and v7

Compare unsigned greater than or equal

vcgeq_u16Experimentalneon and v7

Compare unsigned greater than or equal

vcgeq_u32Experimentalneon and v7

Compare unsigned greater than or equal

vcgt_f32Experimentalneon and v7

Floating-point compare greater than

vcgt_s8Experimentalneon and v7

Compare signed greater than

vcgt_s16Experimentalneon and v7

Compare signed greater than

vcgt_s32Experimentalneon and v7

Compare signed greater than

vcgt_u8Experimentalneon and v7

Compare unsigned highe

vcgt_u16Experimentalneon and v7

Compare unsigned highe

vcgt_u32Experimentalneon and v7

Compare unsigned highe

vcgtq_f32Experimentalneon and v7

Floating-point compare greater than

vcgtq_s8Experimentalneon and v7

Compare signed greater than

vcgtq_s16Experimentalneon and v7

Compare signed greater than

vcgtq_s32Experimentalneon and v7

Compare signed greater than

vcgtq_u8Experimentalneon and v7

Compare unsigned highe

vcgtq_u16Experimentalneon and v7

Compare unsigned highe

vcgtq_u32Experimentalneon and v7

Compare unsigned highe

vcle_f32Experimentalneon and v7

Floating-point compare less than or equal

vcle_s8Experimentalneon and v7

Compare signed less than or equal

vcle_s16Experimentalneon and v7

Compare signed less than or equal

vcle_s32Experimentalneon and v7

Compare signed less than or equal

vcle_u8Experimentalneon and v7

Compare unsigned less than or equal

vcle_u16Experimentalneon and v7

Compare unsigned less than or equal

vcle_u32Experimentalneon and v7

Compare unsigned less than or equal

vcleq_f32Experimentalneon and v7

Floating-point compare less than or equal

vcleq_s8Experimentalneon and v7

Compare signed less than or equal

vcleq_s16Experimentalneon and v7

Compare signed less than or equal

vcleq_s32Experimentalneon and v7

Compare signed less than or equal

vcleq_u8Experimentalneon and v7

Compare unsigned less than or equal

vcleq_u16Experimentalneon and v7

Compare unsigned less than or equal

vcleq_u32Experimentalneon and v7

Compare unsigned less than or equal

vclt_f32Experimentalneon and v7

Floating-point compare less than

vclt_s8Experimentalneon and v7

Compare signed less than

vclt_s16Experimentalneon and v7

Compare signed less than

vclt_s32Experimentalneon and v7

Compare signed less than

vclt_u8Experimentalneon and v7

Compare unsigned less than

vclt_u16Experimentalneon and v7

Compare unsigned less than

vclt_u32Experimentalneon and v7

Compare unsigned less than

vcltq_f32Experimentalneon and v7

Floating-point compare less than

vcltq_s8Experimentalneon and v7

Compare signed less than

vcltq_s16Experimentalneon and v7

Compare signed less than

vcltq_s32Experimentalneon and v7

Compare signed less than

vcltq_u8Experimentalneon and v7

Compare unsigned less than

vcltq_u16Experimentalneon and v7

Compare unsigned less than

vcltq_u32Experimentalneon and v7

Compare unsigned less than

vcnt_p8Experimentalneon and v7

Population count per byte.

vcnt_s8Experimentalneon and v7

Population count per byte.

vcnt_u8Experimentalneon and v7

Population count per byte.

vcntq_p8Experimentalneon and v7

Population count per byte.

vcntq_s8Experimentalneon and v7

Population count per byte.

vcntq_u8Experimentalneon and v7

Population count per byte.

vcvtq_s32_f32Experimentalneon and v7

Floating-point Convert to Signed fixed-point, rounding toward Zero (vector)

vcvtq_u32_f32Experimentalneon and v7

Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector)

vdupq_n_s8Experimentalneon and v7

Duplicate vector element to vector or scalar

vdupq_n_u8Experimentalneon and v7

Duplicate vector element to vector or scalar

veor_s8Experimentalneon and v7

Vector bitwise exclusive or (vector)

veor_s16Experimentalneon and v7

Vector bitwise exclusive or (vector)

veor_s32Experimentalneon and v7

Vector bitwise exclusive or (vector)

veor_s64Experimentalneon and v7

Vector bitwise exclusive or (vector)

veor_u8Experimentalneon and v7

Vector bitwise exclusive or (vector)

veor_u16Experimentalneon and v7

Vector bitwise exclusive or (vector)

veor_u32Experimentalneon and v7

Vector bitwise exclusive or (vector)

veor_u64Experimentalneon and v7

Vector bitwise exclusive or (vector)

veorq_s8Experimentalneon and v7

Vector bitwise exclusive or (vector)

veorq_s16Experimentalneon and v7

Vector bitwise exclusive or (vector)

veorq_s32Experimentalneon and v7

Vector bitwise exclusive or (vector)

veorq_s64Experimentalneon and v7

Vector bitwise exclusive or (vector)

veorq_u8Experimentalneon and v7

Vector bitwise exclusive or (vector)

veorq_u16Experimentalneon and v7

Vector bitwise exclusive or (vector)

veorq_u32Experimentalneon and v7

Vector bitwise exclusive or (vector)

veorq_u64Experimentalneon and v7

Vector bitwise exclusive or (vector)

vextq_s8Experimentalneon and v7

Extract vector from pair of vectors

vextq_u8Experimentalneon and v7

Extract vector from pair of vectors

vget_lane_u8Experimentalneon and v7

Move vector element to general-purpose register

vget_lane_u64Experimentalneon and v7

Move vector element to general-purpose register

vgetq_lane_s32Experimentalneon and v7

Move vector element to general-purpose register

vgetq_lane_u16Experimentalneon and v7

Move vector element to general-purpose register

vgetq_lane_u32Experimentalneon and v7

Move vector element to general-purpose register

vgetq_lane_u64Experimentalneon and v7

Move vector element to general-purpose register

vhadd_s8Experimentalneon and v7

Halving add

vhadd_s16Experimentalneon and v7

Halving add

vhadd_s32Experimentalneon and v7

Halving add

vhadd_u8Experimentalneon and v7

Halving add

vhadd_u16Experimentalneon and v7

Halving add

vhadd_u32Experimentalneon and v7

Halving add

vhaddq_s8Experimentalneon and v7

Halving add

vhaddq_s16Experimentalneon and v7

Halving add

vhaddq_s32Experimentalneon and v7

Halving add

vhaddq_u8Experimentalneon and v7

Halving add

vhaddq_u16Experimentalneon and v7

Halving add

vhaddq_u32Experimentalneon and v7

Halving add

vhsub_s8Experimentalneon and v7

Signed halving subtract

vhsub_s16Experimentalneon and v7

Signed halving subtract

vhsub_s32Experimentalneon and v7

Signed halving subtract

vhsub_u8Experimentalneon and v7

Signed halving subtract

vhsub_u16Experimentalneon and v7

Signed halving subtract

vhsub_u32Experimentalneon and v7

Signed halving subtract

vhsubq_s8Experimentalneon and v7

Signed halving subtract

vhsubq_s16Experimentalneon and v7

Signed halving subtract

vhsubq_s32Experimentalneon and v7

Signed halving subtract

vhsubq_u8Experimentalneon and v7

Signed halving subtract

vhsubq_u16Experimentalneon and v7

Signed halving subtract

vhsubq_u32Experimentalneon and v7

Signed halving subtract

vld1_dup_f32Experimentalneon and v7

Load one single-element structure and Replicate to all lanes (of one register).

vld1_dup_p8Experimentalneon and v7

Load one single-element structure and Replicate to all lanes (of one register).

vld1_dup_p16Experimentalneon and v7

Load one single-element structure and Replicate to all lanes (of one register).

vld1_dup_s8Experimentalneon and v7

Load one single-element structure and Replicate to all lanes (of one register).

vld1_dup_s16Experimentalneon and v7

Load one single-element structure and Replicate to all lanes (of one register).

vld1_dup_s32Experimentalneon and v7

Load one single-element structure and Replicate to all lanes (of one register).

vld1_dup_s64Experimentalneon and v7

Load one single-element structure and Replicate to all lanes (of one register).

vld1_dup_u8Experimentalneon and v7

Load one single-element structure and Replicate to all lanes (of one register).

vld1_dup_u16Experimentalneon and v7

Load one single-element structure and Replicate to all lanes (of one register).

vld1_dup_u32Experimentalneon and v7

Load one single-element structure and Replicate to all lanes (of one register).

vld1_dup_u64Experimentalneon and v7

Load one single-element structure and Replicate to all lanes (of one register).

vld1_f32Experimentalneon,v7

Load multiple single-element structures to one, two, three, or four registers.

vld1_lane_f32Experimentalneon and v7

Load one single-element structure to one lane of one register.

vld1_lane_p8Experimentalneon and v7

Load one single-element structure to one lane of one register.

vld1_lane_p16Experimentalneon and v7

Load one single-element structure to one lane of one register.

vld1_lane_s8Experimentalneon and v7

Load one single-element structure to one lane of one register.

vld1_lane_s16Experimentalneon and v7

Load one single-element structure to one lane of one register.

vld1_lane_s32Experimentalneon and v7

Load one single-element structure to one lane of one register.

vld1_lane_s64Experimentalneon and v7

Load one single-element structure to one lane of one register.

vld1_lane_u8Experimentalneon and v7

Load one single-element structure to one lane of one register.

vld1_lane_u16Experimentalneon and v7

Load one single-element structure to one lane of one register.

vld1_lane_u32Experimentalneon and v7

Load one single-element structure to one lane of one register.

vld1_lane_u64Experimentalneon and v7

Load one single-element structure to one lane of one register.

vld1_p8Experimentalneon,v7

Load multiple single-element structures to one, two, three, or four registers.

vld1_p16Experimentalneon,v7

Load multiple single-element structures to one, two, three, or four registers.

vld1_s8Experimentalneon,v7

Load multiple single-element structures to one, two, three, or four registers.

vld1_s16Experimentalneon,v7

Load multiple single-element structures to one, two, three, or four registers.

vld1_s32Experimentalneon,v7

Load multiple single-element structures to one, two, three, or four registers.

vld1_s64Experimentalneon,v7

Load multiple single-element structures to one, two, three, or four registers.

vld1_u8Experimentalneon,v7

Load multiple single-element structures to one, two, three, or four registers.

vld1_u16Experimentalneon,v7

Load multiple single-element structures to one, two, three, or four registers.

vld1_u32Experimentalneon,v7

Load multiple single-element structures to one, two, three, or four registers.

vld1_u64Experimentalneon,v7

Load multiple single-element structures to one, two, three, or four registers.

vld1q_dup_f32Experimentalneon and v7

Load one single-element structure and Replicate to all lanes (of one register).

vld1q_dup_p8Experimentalneon and v7

Load one single-element structure and Replicate to all lanes (of one register).

vld1q_dup_p16Experimentalneon and v7

Load one single-element structure and Replicate to all lanes (of one register).

vld1q_dup_s8Experimentalneon and v7

Load one single-element structure and Replicate to all lanes (of one register).

vld1q_dup_s16Experimentalneon and v7

Load one single-element structure and Replicate to all lanes (of one register).

vld1q_dup_s32Experimentalneon and v7

Load one single-element structure and Replicate to all lanes (of one register).

vld1q_dup_s64Experimentalneon and v7

Load one single-element structure and Replicate to all lanes (of one register).

vld1q_dup_u8Experimentalneon and v7

Load one single-element structure and Replicate to all lanes (of one register).

vld1q_dup_u16Experimentalneon and v7

Load one single-element structure and Replicate to all lanes (of one register).

vld1q_dup_u32Experimentalneon and v7

Load one single-element structure and Replicate to all lanes (of one register).

vld1q_dup_u64Experimentalneon and v7

Load one single-element structure and Replicate to all lanes (of one register).

vld1q_f32Experimentalneon,v7

Load multiple single-element structures to one, two, three, or four registers.

vld1q_lane_f32Experimentalneon and v7

Load one single-element structure to one lane of one register.

vld1q_lane_p8Experimentalneon and v7

Load one single-element structure to one lane of one register.

vld1q_lane_p16Experimentalneon and v7

Load one single-element structure to one lane of one register.

vld1q_lane_s8Experimentalneon and v7

Load one single-element structure to one lane of one register.

vld1q_lane_s16Experimentalneon and v7

Load one single-element structure to one lane of one register.

vld1q_lane_s32Experimentalneon and v7

Load one single-element structure to one lane of one register.

vld1q_lane_s64Experimentalneon and v7

Load one single-element structure to one lane of one register.

vld1q_lane_u8Experimentalneon and v7

Load one single-element structure to one lane of one register.

vld1q_lane_u16Experimentalneon and v7

Load one single-element structure to one lane of one register.

vld1q_lane_u32Experimentalneon and v7

Load one single-element structure to one lane of one register.

vld1q_lane_u64Experimentalneon and v7

Load one single-element structure to one lane of one register.

vld1q_p8Experimentalneon,v7

Load multiple single-element structures to one, two, three, or four registers.

vld1q_p16Experimentalneon,v7

Load multiple single-element structures to one, two, three, or four registers.

vld1q_s8Experimentalneon,v7

Load multiple single-element structures to one, two, three, or four registers.

vld1q_s16Experimentalneon,v7

Load multiple single-element structures to one, two, three, or four registers.

vld1q_s32Experimentalneon,v7

Load multiple single-element structures to one, two, three, or four registers.

vld1q_s64Experimentalneon,v7

Load multiple single-element structures to one, two, three, or four registers.

vld1q_u8Experimentalneon,v7

Load multiple single-element structures to one, two, three, or four registers.

vld1q_u16Experimentalneon,v7

Load multiple single-element structures to one, two, three, or four registers.

vld1q_u32Experimentalneon,v7

Load multiple single-element structures to one, two, three, or four registers.

vld1q_u64Experimentalneon,v7

Load multiple single-element structures to one, two, three, or four registers.

vmax_f32Experimentalneon and v7

Maximum (vector)

vmax_s8Experimentalneon and v7

Maximum (vector)

vmax_s16Experimentalneon and v7

Maximum (vector)

vmax_s32Experimentalneon and v7

Maximum (vector)

vmax_u8Experimentalneon and v7

Maximum (vector)

vmax_u16Experimentalneon and v7

Maximum (vector)

vmax_u32Experimentalneon and v7

Maximum (vector)

vmaxq_f32Experimentalneon and v7

Maximum (vector)

vmaxq_s8Experimentalneon and v7

Maximum (vector)

vmaxq_s16Experimentalneon and v7

Maximum (vector)

vmaxq_s32Experimentalneon and v7

Maximum (vector)

vmaxq_u8Experimentalneon and v7

Maximum (vector)

vmaxq_u16Experimentalneon and v7

Maximum (vector)

vmaxq_u32Experimentalneon and v7

Maximum (vector)

vmin_f32Experimentalneon and v7

Minimum (vector)

vmin_s8Experimentalneon and v7

Minimum (vector)

vmin_s16Experimentalneon and v7

Minimum (vector)

vmin_s32Experimentalneon and v7

Minimum (vector)

vmin_u8Experimentalneon and v7

Minimum (vector)

vmin_u16Experimentalneon and v7

Minimum (vector)

vmin_u32Experimentalneon and v7

Minimum (vector)

vminq_f32Experimentalneon and v7

Minimum (vector)

vminq_s8Experimentalneon and v7

Minimum (vector)

vminq_s16Experimentalneon and v7

Minimum (vector)

vminq_s32Experimentalneon and v7

Minimum (vector)

vminq_u8Experimentalneon and v7

Minimum (vector)

vminq_u16Experimentalneon and v7

Minimum (vector)

vminq_u32Experimentalneon and v7

Minimum (vector)

vmovl_s8Experimentalneon and v7

Vector long move.

vmovl_s16Experimentalneon and v7

Vector long move.

vmovl_s32Experimentalneon and v7

Vector long move.

vmovl_u8Experimentalneon and v7

Vector long move.

vmovl_u16Experimentalneon and v7

Vector long move.

vmovl_u32Experimentalneon and v7

Vector long move.

vmovn_s16Experimentalneon and v7

Vector narrow integer.

vmovn_s32Experimentalneon and v7

Vector narrow integer.

vmovn_s64Experimentalneon and v7

Vector narrow integer.

vmovn_u16Experimentalneon and v7

Vector narrow integer.

vmovn_u32Experimentalneon and v7

Vector narrow integer.

vmovn_u64Experimentalneon and v7

Vector narrow integer.

vmovq_n_u8Experimentalneon and v7

Duplicate vector element to vector or scalar

vmul_f32Experimentalneon and v7

Multiply

vmul_s8Experimentalneon and v7

Multiply

vmul_s16Experimentalneon and v7

Multiply

vmul_s32Experimentalneon and v7

Multiply

vmul_u8Experimentalneon and v7

Multiply

vmul_u16Experimentalneon and v7

Multiply

vmul_u32Experimentalneon and v7

Multiply

vmulq_f32Experimentalneon and v7

Multiply

vmulq_s8Experimentalneon and v7

Multiply

vmulq_s16Experimentalneon and v7

Multiply

vmulq_s32Experimentalneon and v7

Multiply

vmulq_u8Experimentalneon and v7

Multiply

vmulq_u16Experimentalneon and v7

Multiply

vmulq_u32Experimentalneon and v7

Multiply

vmvn_p8Experimentalneon and v7

Vector bitwise not.

vmvn_s8Experimentalneon and v7

Vector bitwise not.

vmvn_s16Experimentalneon and v7

Vector bitwise not.

vmvn_s32Experimentalneon and v7

Vector bitwise not.

vmvn_u8Experimentalneon and v7

Vector bitwise not.

vmvn_u16Experimentalneon and v7

Vector bitwise not.

vmvn_u32Experimentalneon and v7

Vector bitwise not.

vmvnq_p8Experimentalneon and v7

Vector bitwise not.

vmvnq_s8Experimentalneon and v7

Vector bitwise not.

vmvnq_s16Experimentalneon and v7

Vector bitwise not.

vmvnq_s32Experimentalneon and v7

Vector bitwise not.

vmvnq_u8Experimentalneon and v7

Vector bitwise not.

vmvnq_u16Experimentalneon and v7

Vector bitwise not.

vmvnq_u32Experimentalneon and v7

Vector bitwise not.

vorr_s8Experimentalneon and v7

Vector bitwise or (immediate, inclusive)

vorr_s16Experimentalneon and v7

Vector bitwise or (immediate, inclusive)

vorr_s32Experimentalneon and v7

Vector bitwise or (immediate, inclusive)

vorr_s64Experimentalneon and v7

Vector bitwise or (immediate, inclusive)

vorr_u8Experimentalneon and v7

Vector bitwise or (immediate, inclusive)

vorr_u16Experimentalneon and v7

Vector bitwise or (immediate, inclusive)

vorr_u32Experimentalneon and v7

Vector bitwise or (immediate, inclusive)

vorr_u64Experimentalneon and v7

Vector bitwise or (immediate, inclusive)

vorrq_s8Experimentalneon and v7

Vector bitwise or (immediate, inclusive)

vorrq_s16Experimentalneon and v7

Vector bitwise or (immediate, inclusive)

vorrq_s32Experimentalneon and v7

Vector bitwise or (immediate, inclusive)

vorrq_s64Experimentalneon and v7

Vector bitwise or (immediate, inclusive)

vorrq_u8Experimentalneon and v7

Vector bitwise or (immediate, inclusive)

vorrq_u16Experimentalneon and v7

Vector bitwise or (immediate, inclusive)

vorrq_u32Experimentalneon and v7

Vector bitwise or (immediate, inclusive)

vorrq_u64Experimentalneon and v7

Vector bitwise or (immediate, inclusive)

vpadal_s8Experimentalneon and v7

Signed Add and Accumulate Long Pairwise.

vpadal_s16Experimentalneon and v7

Signed Add and Accumulate Long Pairwise.

vpadal_s32Experimentalneon and v7

Signed Add and Accumulate Long Pairwise.

vpadal_u8Experimentalneon and v7

Unsigned Add and Accumulate Long Pairwise.

vpadal_u16Experimentalneon and v7

Unsigned Add and Accumulate Long Pairwise.

vpadal_u32Experimentalneon and v7

Unsigned Add and Accumulate Long Pairwise.

vpadalq_s8Experimentalneon and v7

Signed Add and Accumulate Long Pairwise.

vpadalq_s16Experimentalneon and v7

Signed Add and Accumulate Long Pairwise.

vpadalq_s32Experimentalneon and v7

Signed Add and Accumulate Long Pairwise.

vpadalq_u8Experimentalneon and v7

Unsigned Add and Accumulate Long Pairwise.

vpadalq_u16Experimentalneon and v7

Unsigned Add and Accumulate Long Pairwise.

vpadalq_u32Experimentalneon and v7

Unsigned Add and Accumulate Long Pairwise.

vpadd_s8Experimentalneon and v7

Add pairwise.

vpadd_s16Experimentalneon and v7

Add pairwise.

vpadd_s32Experimentalneon and v7

Add pairwise.

vpadd_u8Experimentalneon and v7

Add pairwise.

vpadd_u16Experimentalneon and v7

Add pairwise.

vpadd_u32Experimentalneon and v7

Add pairwise.

vpaddl_s8Experimentalneon and v7

Signed Add Long Pairwise.

vpaddl_s16Experimentalneon and v7

Signed Add Long Pairwise.

vpaddl_s32Experimentalneon and v7

Signed Add Long Pairwise.

vpaddl_u8Experimentalneon and v7

Unsigned Add Long Pairwise.

vpaddl_u16Experimentalneon and v7

Unsigned Add Long Pairwise.

vpaddl_u32Experimentalneon and v7

Unsigned Add Long Pairwise.

vpaddlq_s8Experimentalneon and v7

Signed Add Long Pairwise.

vpaddlq_s16Experimentalneon and v7

Signed Add Long Pairwise.

vpaddlq_s32Experimentalneon and v7

Signed Add Long Pairwise.

vpaddlq_u8Experimentalneon and v7

Unsigned Add Long Pairwise.

vpaddlq_u16Experimentalneon and v7

Unsigned Add Long Pairwise.

vpaddlq_u32Experimentalneon and v7

Unsigned Add Long Pairwise.

vpmax_f32Experimentalneon and v7

Folding maximum of adjacent pairs

vpmax_s8Experimentalneon and v7

Folding maximum of adjacent pairs

vpmax_s16Experimentalneon and v7

Folding maximum of adjacent pairs

vpmax_s32Experimentalneon and v7

Folding maximum of adjacent pairs

vpmax_u8Experimentalneon and v7

Folding maximum of adjacent pairs

vpmax_u16Experimentalneon and v7

Folding maximum of adjacent pairs

vpmax_u32Experimentalneon and v7

Folding maximum of adjacent pairs

vpmin_f32Experimentalneon and v7

Folding minimum of adjacent pairs

vpmin_s8Experimentalneon and v7

Folding minimum of adjacent pairs

vpmin_s16Experimentalneon and v7

Folding minimum of adjacent pairs

vpmin_s32Experimentalneon and v7

Folding minimum of adjacent pairs

vpmin_u8Experimentalneon and v7

Folding minimum of adjacent pairs

vpmin_u16Experimentalneon and v7

Folding minimum of adjacent pairs

vpmin_u32Experimentalneon and v7

Folding minimum of adjacent pairs

vqadd_s8Experimentalneon and v7

Saturating add

vqadd_s16Experimentalneon and v7

Saturating add

vqadd_s32Experimentalneon and v7

Saturating add

vqadd_u8Experimentalneon and v7

Saturating add

vqadd_u16Experimentalneon and v7

Saturating add

vqadd_u32Experimentalneon and v7

Saturating add

vqaddq_s8Experimentalneon and v7

Saturating add

vqaddq_s16Experimentalneon and v7

Saturating add

vqaddq_s32Experimentalneon and v7

Saturating add

vqaddq_u8Experimentalneon and v7

Saturating add

vqaddq_u16Experimentalneon and v7

Saturating add

vqaddq_u32Experimentalneon and v7

Saturating add

vqmovn_u64Experimentalneon and v7

Unsigned saturating extract narrow.

vqsub_s8Experimentalneon and v7

Saturating subtract

vqsub_s16Experimentalneon and v7

Saturating subtract

vqsub_s32Experimentalneon and v7

Saturating subtract

vqsub_u8Experimentalneon and v7

Saturating subtract

vqsub_u16Experimentalneon and v7

Saturating subtract

vqsub_u32Experimentalneon and v7

Saturating subtract

vqsubq_s8Experimentalneon and v7

Saturating subtract

vqsubq_s16Experimentalneon and v7

Saturating subtract

vqsubq_s32Experimentalneon and v7

Saturating subtract

vqsubq_u8Experimentalneon and v7

Saturating subtract

vqsubq_u16Experimentalneon and v7

Saturating subtract

vqsubq_u32Experimentalneon and v7

Saturating subtract

vraddhn_high_s16Experimentalneon and v7

Rounding Add returning High Narrow (high half).

vraddhn_high_s32Experimentalneon and v7

Rounding Add returning High Narrow (high half).

vraddhn_high_s64Experimentalneon and v7

Rounding Add returning High Narrow (high half).

vraddhn_high_u16Experimentalneon and v7

Rounding Add returning High Narrow (high half).

vraddhn_high_u32Experimentalneon and v7

Rounding Add returning High Narrow (high half).

vraddhn_high_u64Experimentalneon and v7

Rounding Add returning High Narrow (high half).

vraddhn_s16Experimentalneon and v7

Rounding Add returning High Narrow.

vraddhn_s32Experimentalneon and v7

Rounding Add returning High Narrow.

vraddhn_s64Experimentalneon and v7

Rounding Add returning High Narrow.

vraddhn_u16Experimentalneon and v7

Rounding Add returning High Narrow.

vraddhn_u32Experimentalneon and v7

Rounding Add returning High Narrow.

vraddhn_u64Experimentalneon and v7

Rounding Add returning High Narrow.

vreinterpret_u64_u32Experimentalneon and v7

Vector reinterpret cast operation

vreinterpretq_s8_u8Experimentalneon and v7

Vector reinterpret cast operation

vreinterpretq_u8_s8Experimentalneon and v7

Vector reinterpret cast operation

vreinterpretq_u16_u8Experimentalneon and v7

Vector reinterpret cast operation

vreinterpretq_u32_u8Experimentalneon and v7

Vector reinterpret cast operation

vreinterpretq_u64_u8Experimentalneon and v7

Vector reinterpret cast operation

vrev16_p8Experimentalneon and v7

Reversing vector elements (swap endianness)

vrev16_s8Experimentalneon and v7

Reversing vector elements (swap endianness)

vrev16_u8Experimentalneon and v7

Reversing vector elements (swap endianness)

vrev16q_p8Experimentalneon and v7

Reversing vector elements (swap endianness)

vrev16q_s8Experimentalneon and v7

Reversing vector elements (swap endianness)

vrev16q_u8Experimentalneon and v7

Reversing vector elements (swap endianness)

vrev32_p8Experimentalneon and v7

Reversing vector elements (swap endianness)

vrev32_s8Experimentalneon and v7

Reversing vector elements (swap endianness)

vrev32_u8Experimentalneon and v7

Reversing vector elements (swap endianness)

vrev32_u16Experimentalneon and v7

Reversing vector elements (swap endianness)

vrev32q_p8Experimentalneon and v7

Reversing vector elements (swap endianness)

vrev32q_s8Experimentalneon and v7

Reversing vector elements (swap endianness)

vrev32q_u8Experimentalneon and v7

Reversing vector elements (swap endianness)

vrev32q_u16Experimentalneon and v7

Reversing vector elements (swap endianness)

vrev64_f32Experimentalneon and v7

Reversing vector elements (swap endianness)

vrev64_p8Experimentalneon and v7

Reversing vector elements (swap endianness)

vrev64_p16Experimentalneon and v7

Reversing vector elements (swap endianness)

vrev64_s8Experimentalneon and v7

Reversing vector elements (swap endianness)

vrev64_s16Experimentalneon and v7

Reversing vector elements (swap endianness)

vrev64_s32Experimentalneon and v7

Reversing vector elements (swap endianness)

vrev64_u8Experimentalneon and v7

Reversing vector elements (swap endianness)

vrev64_u16Experimentalneon and v7

Reversing vector elements (swap endianness)

vrev64_u32Experimentalneon and v7

Reversing vector elements (swap endianness)

vrev64q_f32Experimentalneon and v7

Reversing vector elements (swap endianness)

vrev64q_p8Experimentalneon and v7

Reversing vector elements (swap endianness)

vrev64q_p16Experimentalneon and v7

Reversing vector elements (swap endianness)

vrev64q_s8Experimentalneon and v7

Reversing vector elements (swap endianness)

vrev64q_s16Experimentalneon and v7

Reversing vector elements (swap endianness)

vrev64q_s32Experimentalneon and v7

Reversing vector elements (swap endianness)

vrev64q_u8Experimentalneon and v7

Reversing vector elements (swap endianness)

vrev64q_u16Experimentalneon and v7

Reversing vector elements (swap endianness)

vrev64q_u32Experimentalneon and v7

Reversing vector elements (swap endianness)

vrhadd_s8Experimentalneon and v7

Rounding halving add

vrhadd_s16Experimentalneon and v7

Rounding halving add

vrhadd_s32Experimentalneon and v7

Rounding halving add

vrhadd_u8Experimentalneon and v7

Rounding halving add

vrhadd_u16Experimentalneon and v7

Rounding halving add

vrhadd_u32Experimentalneon and v7

Rounding halving add

vrhaddq_s8Experimentalneon and v7

Rounding halving add

vrhaddq_s16Experimentalneon and v7

Rounding halving add

vrhaddq_s32Experimentalneon and v7

Rounding halving add

vrhaddq_u8Experimentalneon and v7

Rounding halving add

vrhaddq_u16Experimentalneon and v7

Rounding halving add

vrhaddq_u32Experimentalneon and v7

Rounding halving add

vrsqrte_f32Experimentalneon

Reciprocal square-root estimate.

vshlq_n_u8Experimentalneon and v7

Shift right

vshrq_n_u8Experimentalneon and v7

Unsigned shift right

vsli_n_p8Experimentalneon,v7

Shift Left and Insert (immediate)

vsli_n_p16Experimentalneon,v7

Shift Left and Insert (immediate)

vsli_n_s8Experimentalneon,v7

Shift Left and Insert (immediate)

vsli_n_s16Experimentalneon,v7

Shift Left and Insert (immediate)

vsli_n_s32Experimentalneon,v7

Shift Left and Insert (immediate)

vsli_n_s64Experimentalneon,v7

Shift Left and Insert (immediate)

vsli_n_u8Experimentalneon,v7

Shift Left and Insert (immediate)

vsli_n_u16Experimentalneon,v7

Shift Left and Insert (immediate)

vsli_n_u32Experimentalneon,v7

Shift Left and Insert (immediate)

vsli_n_u64Experimentalneon,v7

Shift Left and Insert (immediate)

vsliq_n_p8Experimentalneon,v7

Shift Left and Insert (immediate)

vsliq_n_p16Experimentalneon,v7

Shift Left and Insert (immediate)

vsliq_n_s8Experimentalneon,v7

Shift Left and Insert (immediate)

vsliq_n_s16Experimentalneon,v7

Shift Left and Insert (immediate)

vsliq_n_s32Experimentalneon,v7

Shift Left and Insert (immediate)

vsliq_n_s64Experimentalneon,v7

Shift Left and Insert (immediate)

vsliq_n_u8Experimentalneon,v7

Shift Left and Insert (immediate)

vsliq_n_u16Experimentalneon,v7

Shift Left and Insert (immediate)

vsliq_n_u32Experimentalneon,v7

Shift Left and Insert (immediate)

vsliq_n_u64Experimentalneon,v7

Shift Left and Insert (immediate)

vsri_n_p8Experimentalneon,v7

Shift Right and Insert (immediate)

vsri_n_p16Experimentalneon,v7

Shift Right and Insert (immediate)

vsri_n_s8Experimentalneon,v7

Shift Right and Insert (immediate)

vsri_n_s16Experimentalneon,v7

Shift Right and Insert (immediate)

vsri_n_s32Experimentalneon,v7

Shift Right and Insert (immediate)

vsri_n_s64Experimentalneon,v7

Shift Right and Insert (immediate)

vsri_n_u8Experimentalneon,v7

Shift Right and Insert (immediate)

vsri_n_u16Experimentalneon,v7

Shift Right and Insert (immediate)

vsri_n_u32Experimentalneon,v7

Shift Right and Insert (immediate)

vsri_n_u64Experimentalneon,v7

Shift Right and Insert (immediate)

vsriq_n_p8Experimentalneon,v7

Shift Right and Insert (immediate)

vsriq_n_p16Experimentalneon,v7

Shift Right and Insert (immediate)

vsriq_n_s8Experimentalneon,v7

Shift Right and Insert (immediate)

vsriq_n_s16Experimentalneon,v7

Shift Right and Insert (immediate)

vsriq_n_s32Experimentalneon,v7

Shift Right and Insert (immediate)

vsriq_n_s64Experimentalneon,v7

Shift Right and Insert (immediate)

vsriq_n_u8Experimentalneon,v7

Shift Right and Insert (immediate)

vsriq_n_u16Experimentalneon,v7

Shift Right and Insert (immediate)

vsriq_n_u32Experimentalneon,v7

Shift Right and Insert (immediate)

vsriq_n_u64Experimentalneon,v7

Shift Right and Insert (immediate)

vsub_f32Experimentalneon and v7

Subtract

vsub_s8Experimentalneon and v7

Subtract

vsub_s16Experimentalneon and v7

Subtract

vsub_s32Experimentalneon and v7

Subtract

vsub_s64Experimentalneon and v7

Subtract

vsub_u8Experimentalneon and v7

Subtract

vsub_u16Experimentalneon and v7

Subtract

vsub_u32Experimentalneon and v7

Subtract

vsub_u64Experimentalneon and v7

Subtract

vsubq_f32Experimentalneon and v7

Subtract

vsubq_s8Experimentalneon and v7

Subtract

vsubq_s16Experimentalneon and v7

Subtract

vsubq_s32Experimentalneon and v7

Subtract

vsubq_s64Experimentalneon and v7

Subtract

vsubq_u8Experimentalneon and v7

Subtract

vsubq_u16Experimentalneon and v7

Subtract

vsubq_u32Experimentalneon and v7

Subtract

vsubq_u64Experimentalneon and v7

Subtract

vtbl1_p8Experimentalneon,v7

Table look-up

vtbl1_s8Experimentalneon,v7

Table look-up

vtbl1_u8Experimentalneon,v7

Table look-up

vtbl2_p8Experimentalneon,v7

Table look-up

vtbl2_s8Experimentalneon,v7

Table look-up

vtbl2_u8Experimentalneon,v7

Table look-up

vtbl3_p8Experimentalneon,v7

Table look-up

vtbl3_s8Experimentalneon,v7

Table look-up

vtbl3_u8Experimentalneon,v7

Table look-up

vtbl4_p8Experimentalneon,v7

Table look-up

vtbl4_s8Experimentalneon,v7

Table look-up

vtbl4_u8Experimentalneon,v7

Table look-up

vtbx1_p8Experimentalneon,v7

Extended table look-up

vtbx1_s8Experimentalneon,v7

Extended table look-up

vtbx1_u8Experimentalneon,v7

Extended table look-up

vtbx2_p8Experimentalneon,v7

Extended table look-up

vtbx2_s8Experimentalneon,v7

Extended table look-up

vtbx2_u8Experimentalneon,v7

Extended table look-up

vtbx3_p8Experimentalneon,v7

Extended table look-up

vtbx3_s8Experimentalneon,v7

Extended table look-up

vtbx3_u8Experimentalneon,v7

Extended table look-up

vtbx4_p8Experimentalneon,v7

Extended table look-up

vtbx4_s8Experimentalneon,v7

Extended table look-up

vtbx4_u8Experimentalneon,v7

Extended table look-up